1. Field of the Invention
The present invention relates to a prober that performs an electrical inspection of multiple chips formed on a semiconductor wafer.
2. Description of the Related Art
In a semiconductor manufacturing process, various kinds of processing are applied to a thin disc-like semiconductor wafer, and multiple chips (dies) each having a semiconductor apparatus (device) are formed. The electrical characteristic of each chip is inspected, and then, after each chip is subsequently separated by a dicer, it is fixed to a lead frame or the like and assembled. The above-mentioned electrical characteristic inspection is performed by a wafer test system composed of a prober and a tester. The prober fixes a wafer to a wafer chuck and a probe is brought into contact with an electrode of each chip. For electrical inspection, the tester is electrically connected with the probe, applies current and voltage to each chip and measures the characteristic.
In semiconductor apparatuses (devices) such as a power transistor, a power MOSFET (field effect transistor), an IGBT (Insulated Gate Bipolar Transistor), LED and a semiconductor laser, an electrode (chip front-surface electrode) is generally formed on the front surface of the wafer and also an electrode (chip back-surface electrode) is formed on the back surface of the wafer. For example, in the IGBT, a gate electrode and an emitter electrode are formed on the front surface of the wafer, and a collector electrode is formed on the back surface of the wafer.
In order to conduct wafer level inspection in the above-described wafer in which multiple chips having electrodes on both wafer surfaces are formed, a wafer chuck is provided with a conductive support surface (wafer placement surface) that holds the back surface of the wafer in a state contacting with the back surface and operates as a measurement electrode of the tester. This support surface is electrically connected with the tester through a cable drawn out from the wafer chuck. Further, in a case where inspection is conducted, various kinds of measurement are performed in a state where the wafer is held in the wafer chuck and the probe is brought into contact with the electrode (chip front-surface electrode) of each chip formed on the front surface of the wafer.
However, since a cable that connect between the wafer chuck and the tester is arranged through connection connectors installed in the side surface or back surface or the like of a chassis forming the prober in a state where the cable is drawn inside/outside of the chassis, the cable normally needs to have a length of about 1 to 3 meters. Therefore, since the electrical path formed between the chip back-surface electrode and the tester becomes long to make the resistance and inductance large, there is a problem that a measurement error in high-frequency measurement or dynamic measurement is caused and the wafer level inspection cannot be properly performed at requested accuracy.
As a technique to solve such a problem, for example, Japanese Patent Application Laid-Open No. 2011-138865 discloses a technique that intends the shortening of an electrical path between a chip back-surface electrode and a tester by installing a pogo pin electrically connected with the upper surface of a wafer chuck (chuck stage) in the periphery of the wafer chuck and bringing the pogo pin into contact with a chuck lead board installed in the position facing the upper surface of the wafer chuck.
However, in the technique disclosed in Japanese Patent Application Laid-Open No. 2011-138865, since the pogo pin is fixed to the periphery of the wafer chuck, the length of the electrical path between the chip back-surface electrode and the tester varies depending on the position of a chip to be inspected on the wafer. For example, the length of the above-mentioned electrical path varies between a case where a chip existing in the vicinity of the center of the wafer is inspected and a case where a chip existing in the vicinity of the edge part of the wafer is inspected. Therefore, there is a problem that the resistance and impedance caused in the above-mentioned electrical path vary according to the position of the chip to be inspected on the wafer to adversely affect the high-frequency measurement and the dynamic measurement, and the wafer level inspection cannot be conducted at high accuracy.
Meanwhile, Japanese Patent Application Laid-Open No. 2013-118320 discloses a technique in which a wafer holding portion and a conductive probe contact area are adjacently disposed on the upper surface of a wafer chuck (chuck stage), the probe contact area is electrically conducted to the wafer holding portion, and a front-surface electrode probe and a back-surface electrode probe are disposed so as to be spaced a distance apart from each other in the horizontal direction such that, when the front-surface electrode probe relatively moves in an inspection object wafer, the back-surface probe relatively moves in the probe contact area.
According to the technique disclosed in Japanese Patent Application Laid-Open No. 2013-118320, even if the wafer chuck is moved with respect to the front-surface electrode probe when individual chips on the wafer are sequentially inspected, it is not necessary to move the back-surface electrode probe. Therefore, it is assumed that not only an electrical path between the tester and the front-surface electrode probe but also an electrical path between the tester and the back-surface electrode probe can be maintained to have a constant shortest length at any time, and the wafer level inspection can be conducted at high accuracy.